LTC2314-14 ADC Interface

Next step in building the radio is to prepare to interface with the ADC (LTC2314-14) which is sending the samples in serial stream very much like SPI but has timing requirements in order to trigger the conversion and give sufficient time to complete the conversion. The datasheet is showing three timing diagrams two are pushing the timing to the limits and the third is more relaxed and easier to implement.

The whole conversion cycle is taking 20 clk cycles, 16 cycles to transfer the result of the previous conversion and 4 cycles to allow the actual S/H & SAR process to initiate.

I wrote a small VHDL module which is driving the CSn & SCLK with the proper timing and is capturing the incoming stream. In order to test my IP Core I wrote a (not very accurate) functional model which is trying to imitate the behavior of the actual part and it can send out a constant value (fake ADC acquisition) or a sinus wave made of 16 consecutive samples. (samples are 14Bit unsigned)

I instantiated both modules my IP Core which is acting like a SPI Master and the LTC2314 Model which is acting like a slave and checked if the samples are deserialized correctly.

The Model is synthesizable and can be used inside the FPGA for experiments without having the actual front end attached to the FPGA board. (that was plan anyway)

Next Steps is to put all this on the FPGA and capture some samples internally with ILA (Chip Scope for older people) and see if it works like in simulation.

Code available here but is not debugged yet.

LTC2314_vhdl.zip

Download ZIP • 4KB

That's that "coming back soon with another cartoon" (woody woodpecker show....)

Have Fun!

EI3HWB