Audio Output for the Simple Radio
- Aurash

- Dec 31, 2025
- 1 min read
In order to make experiments we need to be able to hear the audio and I found a PMOD module in one of my boxes which fits perfectly my FPGA board.
The module is question is pictured below

link to the manual
This module is using a I2S digital interface and master clock (MCLK) from the FPGA and can be used with i2C control or standalone (jumpers) I'm using without I2C for the time being in default settings. (256 Fs MCLK, Provide MCLK, Gain 0, Standard i2S)
The module is powered from PMOD (3.3V) and I coupled an 8 Ohm/5W speaker at the output (only one channel)
In order to send audio samples to this PMOD I had to use a I2S interface (bidirectional btw) written in VHDL by "unknown author" is not saying much in the header and I don't remember exactly from where I got the file ...getting old I guess.
The vhdl file below
I did not use a standard audio sampling rate or clock (because is irrelevant for the test) the my MCLK is 28MHz and the MCLK/SCLK ratio is 8. My sample size is 16 bit (signed)

To generate an audio tone I used a DDS programed to generate a sinus/cos amplitude output of 1KHz (16bit signed) The DDS was running from 100MHz clock and the MCLK was totally unrelated but I didn't bother for an audio test, it worked like charm.
I'm not going to publish the whole Vivado project because is too simple and life is short.
More in the following days
73 de EI3HWB.




Super !