In this video I'm showing the process of testing the ADC interface of my ADC DAC FPGA board using some fixed patterns generated by the ADC chip and later on sampling a sinus signal from the signal generator. All working but I had to correct some mistakes that I made along the way (bit swap in the DDR capture registers) and data inversions (the usual stuff) all took half a day.
The vivado project can be downloaded below (Vivado 22.2)
Have fun!
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